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ltc3802 1 3802f n wide v in range: 3v to 30v operation with line feedforward compensation n leading edge modulation architecture for extremely low duty cycle operation n phase-lockable fixed frequency: 330khz to 750khz n two 180 out-of-phase controllers n fast programmable power-up/-down tracking n programmable current limit without external current sense resistor n optional burst mode ? operation at light load n 1% 0.6v voltage reference n external n-channel mosfet architecture n low shutdown current: <100 m a n overvoltage protection and pgood flag n small 28-lead ssop and 32-lead qfn packages dual 550khz synchronous 2-phase dc/dc controller with programmable up/down tracking n notebook and palmtop computers n portable instruments n battery-operated digital devices n dc power distribution systems , ltc and lt are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. u.s. patent nos 5481178, 5846544, 6304066, 6580258, 5055767, 6307356 the ltc ? 3802 is a dual switching regulator controller optimized for high efficiency step-down conversion from input voltages between 3v to 30v. the controller uses a leading edge modulation scheme to allow extremely low duty cycle operation. the constant frequency voltage mode controller allows a phase-lockable frequency between 330khz and 750khz. power loss and noise due to the esr of the input capacitors are minimized by operating the two controller output stages 180 out of phase. the synchro- nous buck architecture automatically shifts to burst mode operation as the output load decreases, ensuring maxi- mum efficiency over a wide range of load currents. the ltc3802 features an onboard, trimmed 0.6v refer- ence and provides better than 1% regulation at the con- verter outputs. a separate output sense provides real time overvoltage protection and pgood sensing. an fbt pin programs the power-up/-down tracking between the two channels to meet various sequencing requirements. a run/ss pin provides soft-start and externally program- mable current limit protection functions. descriptio u features applicatio s u typical applicatio u tg2 boost2 sw2 bg2 pllin plllpf i max2 cmpin2 v cc comp2 fb2 phasemd pgood v inff + + pv cc 0.1 f 0.1 f 10 f cmdsh-3 si7860dp 2 si7860dp 2 4.7 f 25v 8 si7440dp 2 5v cmdsh-3 2200pf 1500pf 560pf 330pf 15k 47k 47k 10k 5v 10 390 15k 5v 390 tg1 boost1 sw1 bg1 pgnd i max1 fbt cmpin1 comp1 fb1 sgnd fcb run/ss 0.1 f b340b b340b 1 h + 330 f 4v 3 56 f 25v 2 v out1 3.3v 15a v in 5v to 22v 10k 10k 2.21k 2.21k 0.47 f v in si7440dp 2 1 h 330 f 4v 3 10k 10k v out2 2.5v 15a 3802 ta01 3.16k 3.16k + 10 f 330pf 560pf 1500pf 2200pf 0.1 f ltc3802 +
ltc3802 2 3802f absolute axi u rati gs w ww u (note 1) consult ltc marketing for parts specified with wider operating temperature ranges. package/order i for atio uu w order part number LTC3802EGN t jmax = 125 c, q ja = 110 c/w t jmax = 125 c, q ja = 34 c/w exposed pad (pin 33) is gnd must be soldered to pcb supply voltage v cc , pv cc ............................................................. 7v boost n .............................................................. 37v boost n C sw n .................................................... 7v sw n ........................................................ C1v to 30v input voltage v inff .................................................................... 30v fb n , cmpin n , fbt, pllin, fcb, run/ss, pgood, plllpf, phasemd, extref, i max n .......................... C0.3v to v cc + 0.3v extended commercial operating temperature range (note 2) .. C40 c to 85 c storage temperature range LTC3802EGN ................................... C 65 c to 150 c ltc3802euh ................................... C 65 c to 125 c lead temperature (soldering, 10 sec) LTC3802EGN only ........................................... 300 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pv cc bg1 boost1 tg1 sw1 pgnd i max1 fbt cmpin1 comp1 fb1 sgnd fcb run/ss bg2 boost2 tg2 sw2 pllin plllpf i max2 cmpin2 v cc comp2 fb2 phasemd v inff pgood uh part marking ltc3802euh order part number 3802 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 sw1 pgnd pgnd i max1 fbt cmpin1 comp1 fb1 pgnd pgnd pllin plllpf i max2 cmpin2 v cc comp2 tg1 boost1 bg1 pv cc bg2 boost2 tg2 sw2 sgnd fcb extref run/ss pgood v inff phasemd fb2 electrical characteristics the l denotes the specifications which apply over the full operating temperature range. (note 3) v cc = pv cc = boost = 5v, unless otherwise specified. symbol parameter conditions min typ max units v cc v cc supply voltage l 356 v pv cc pv cc supply voltage (note 4) l 56 v bv cc boost pin voltage v boost C v sw (note 4) l 56 v v uvlo positive undervoltage lockout measured at v cc 2.2 2.5 2.8 v measured at v inff 2.2 2.5 2.8 v i vcc v cc supply current v fb = v comp l 6.5 9 ma v run/ss = 0v, pllin floating l 100 150 m a
ltc3802 3 3802f electrical characteristics the l denotes the specifications which apply over the full operating temperature range. (note 3) v cc = pv cc = boost = 5v, unless otherwise specified. symbol parameter conditions min typ max units i pvcc pv cc supply current v fb = v cmpin = 0v, no load 2 ma v run/ss = 0v (notes 5, 6) 1 10 m a i boost boost pin current v fb = v cmpin = 0v, no load 1 ma v run/ss = 0v (notes 5, 6) 1 10 m a switcher control loop v fb feedback voltage v extref = 5v, 0 c t 70 c 0.594 0.600 0.606 v v extref = 5v l 0.591 0.600 0.609 v d v fb feedback voltage v cc line regulation v cc = 4.5v to 6v 0.01 %/v d v out output voltage load regulation (note 7) 0.1 0.2 % a err error amp dc gain no load, v extref = v run/ss = v cc l 70 80 db gbw error amp gain bandwidth product f = 100khz (note 7) 10 mhz i comp error amp output sink/source current v run/ss = v cc 12 ma i fb voltage feedback input current v fb = 0v to 1v l 1 m a i cmpin comparators input current v cmpin = 0v to 1v l 1 m a i fbt fbt input current v fbt = 0v to 1v l 1 m a i extref extref input current v extref = 0v to 5v l 1 m a v extref external reference not to affect v fb l 1v a lff d drop in duty cycle/ d v inff v vinff = 5v to 30v 2.3 %/v r vinff v inff input resistance 1m w v pgood positive power good threshold with respect to 0.6v l 5 10 15 % negative power good threshold with respect to 0.6v l C5 C10 C15 % v ovp overvoltage threshold with respect to v fb 359 % v burrs (v cmpin C v fb ) to reset 15 mv burst mode operation C12 mv v saw saw before line compensation 1.2 v i imax i max source current v imax = 1v C9.0 C10 C11.0 m a l C8.5 C10 C11.5 m a i lim(th) i lim comparator offset l C15 0 15 mv v imax /i lim threshold 5v/v hard i lim /i lim threshold v cmpin = 0v 1.5 v/v i ss run/ss source current v cmpin = v fbt = 0.6v, v phasemd = v cc C5 C7 C9 m a run/ss sink/source current ratio v cmpin = v fbt = 0.6v, v phasemd = 0v 1.5 2 2.5 m a/ m a run/ss sink current, i lim v cmpin = v fbt = 0.6v 100 m a run/ss sink current, hard i lim v cmpin = v fbt = 0v l 1ma v shdn run/ss shutdown threshold run/ss - l 0.4 0.8 1.2 v logic and pgood i phasemd phasemd pull-up current v phasemd = 0v C7 m a phasemd pull-down current v phasemd = 5v 2 m a v ih pllin, fcb high level input voltage l 2.4 v v il pllin, fcb low level input voltage l 0.8 v i pgood v pgood leakage current power good 1 m a v olpg v pgood output low voltage i pgood = 1ma l 0.1 0.3 v t pgood v pgood falling edge delay (note 8) l 100 150 m s v pgood rising edge delay (note 8) 10 m s
ltc3802 4 3802f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc3802 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: to ensure proper operation, pv cc and bv cc (v boost C v sw ) must be greater than v gs(on) of the external mosfets. note 5: supply current in normal operation is dominated by the current needed to charge and discharge the external mosfet gates. this current will vary with supply voltage and the external mosfets used. note 6: supply current in shutdown is dominated by external mosfet leakage and may be significantly higher than the quiescent current drawn by the ltc3802, especially at elevated temperature. note 7: guaranteed by design, not subject to test. note 8: rise and fall times are measured using 10% and 90% levels. delay and nonoverlap times are measured using 50% levels. note 9: if v cmpin is less than 90% of its nominal value, bg minimum pulse width is limited to 400ns. note 10: the ltc3802 leading edge modulation architecture does not have a minimum tg pulse width requirement. the tg minimum pulse width is limited by the rise and fall times. electrical characteristics the l denotes the specifications which apply over the full operating temperature range. (note 3) v cc = pv cc = boost = 5v, unless otherwise specified. symbol parameter conditions min typ max units switcher switching characteristics f osc oscillator frequency pllin open or v pllin = 0v 490 550 610 khz v plllpf = 1.2v 550 khz v plllpf = 0v 250 330 400 khz v plllpf = 2.4v 650 750 850 khz r pllin pllin pull-down current source 5 m a i plllpf phase detector output current sourcing capability f pllin > f osc C15 m a sinking capability f pllin < f osc 15 m a phase tg1 vs pllin phasemd floats 0 deg tg1 vs pllin v phasemd = 5v 90 deg tg2 vs pllin phasemd floats 180 deg tg2 vs pllin v phasemd = 5v 270 deg v phasemd shutdown threshold l 1.2 1.7 v floating 2.0 v 90 phase threshold l 3.5 4.0 4.5 v dc min minimum tg duty cycle v pllin = 0v l 0% dc max maximum tg duty cycle v pllin = 0v, v cmpin = 0.6v (note 9) l 86 89 92 % t on(min) tg minimum pulse width (notes 7, 10) 50 ns bg minimum pulse width v cmpin = 0v (note 9) 400 ns t nov driver nonoverlap no load 10 30 80 ns r ds(on) tg high r ds(on) i out = 100ma (note 7) 1.6 2.20 w tg low r ds(on) 1.3 1.80 w bg high r ds(on) 1.8 2.50 w bg low r ds(on) 0.7 1.00 w
ltc3802 5 3802f typical perfor a ce characteristics uw efficiency vs i out i out (a) 0.1 60 efficiency (%) 70 80 1 10 100 3802 g01 50 40 100 90 65 75 85 55 45 95 burst mode operation continuous mode v in = 12v v out = 3.3v t a = 25 c circuit on the first page of this data sheet v in (v) 0 80 efficiency (%) 84 88 92 5 10 15 20 3802 g02 25 96 100 82 86 90 94 98 30 t a = 25 c circuit on the first page of this data sheet v out = 2.5v i out = 5a v out = 2.5v i out = 10a i out (a) 0 v out (v) ? v out (%) 2.4975 2.5025 20 3802 g03 2.4925 2.4875 5 10 15 2.5125 2.5075 ?.1 0.1 ?.3 ?.5 0.5 0.3 ?.2 0 ?.4 0.4 0.2 v in = 12v t a = 25 c circuit on the first page of this data sheet efficiency vs v in load regulation v in (v) 0 v out (v) ? v out (%) 2.5125 2.5075 2.5025 2.4975 2.4925 2.4875 0.5 0.3 0.1 ?.1 ?.3 0.4 0.2 0 ?.2 ?.4 ?.5 5 10 15 20 3802 g04 25 30 v cc = 5v i out = 5a t a = 25 c line regulation temperature ( c) ?0 594.0 v fb (mv) ? v fb (%) 595.2 597.6 598.8 600.0 606.0 602.4 0 50 75 ltc1323 ?tpc05 596.4 603.6 604.8 601.2 ?.0 ?.8 ?.4 ?.2 0 1.0 0.4 ?.6 0.6 0.8 0.2 ?5 25 100 125 v cc = 5v v cc supply voltage (v) 3 597.0 v fb (mv) ? v fb (%) 597.6 598.8 599.4 600.0 603.0 601.2 4 5 5.5 3802 g06 598.2 601.8 602.4 600.6 ?.5 ?.4 ?.2 ?.1 0 0.5 0.2 ?.3 0.3 0.4 0.1 3.5 4.5 6 t a = 25 c v out 2.5v (no load) ac 50mv/div v in 5v to 15v step 5v/div c in : 1 f/50v 6 sanyo 35cv220ax 10 s/div 3802 g07 v comp ac 50mv/div v fb vs temperature v fb vs v cc supply voltage line feedforward transient
ltc3802 6 3802f typical perfor a ce characteristics uw load step in continuous mode burst mode waveform with 0.2a load v out 1.2v 50mv/div i out 1a to 10a step 5a/div 20 s/div v in = 12v circuit on first page of this data sheet 3802 g08 v out 1.2v 50mv/div v sw 10v/div i out 1a to 10a step 5a/div 50 s/div v in = 12v circuit on first page of this data sheet 3802 g09 load step in burst mode operation v out 1.2v 50mv/div v sw 10v/div inductor current 5a/div 50 s/div v in = 12v circuit on first page of this data sheet 3802 g10 burst mode waveform with 3a load v out 1.2v 50mv/div v sw 10v/div inductor current 5a/div 20 s/div v in = 12v circuit on first page of this data sheet 3802 g11 i lim(th) offset vs v imax v imax (mv) 0 i lim(th) offset (mv) 2 6 10 800 3802 g12 ? ? ?0 200 400 600 1000 t a = 25 c v cc = 5v temperature ( c) 50 ?5 ?0 i lim(th) offset (mv) ? 10 0 50 75 3802 g13 ? 6 2 25 100 125 v cc = 5v v imax = 500mv i lim(th) offset vs temperature short-circuit test switching frequency vs temperature tg 10v/div circuit on first page of this data sheet v in = 12v, v out = 3.3v, c ss = 0.01 f, r i(max) = 47k, l = 1 h (toko-fda1254-1rom) run/ss 2v/div inductor current 20a/div 5 s/div 3802 g14 temperature ( c) 50 ?5 500 switching frequency (khz) 540 600 0 50 75 3802 g15 520 580 560 25 100 125 v cc = 5v v cc supply voltage (v) 3 500 switching frequency (khz) 520 540 560 580 600 3.5 4 4.5 5 3802 g16 5.5 6 t a = 25 c switching frequency vs v cc supply voltage
ltc3802 7 3802f typical perfor a ce characteristics uw switching frequency vs v plllpf maximum duty cycle vs temperature continuous mode operation v plllpf (v) 0 250 switching frequency (khz) 350 450 550 650 850 0.4 0.8 1.2 1.6 3802 g17 2 2.4 750 t a = 25 c v cc = 5v v out1 5v ac 20mv/div v out2 1v ac 20mv/div tg1 20v/div tg2 20v/div 0.5 s/div v in = 30v 3802 g18 temperature ( c) ?0 maximum duty cycle (%) 95 25 3802 g19 80 70 ?5 0 50 65 60 100 90 85 75 75 100 125 v cc = 5v f sw = 550khz v cmpin > 0.54v v cmpin < 0.54v maximum duty cycle vs v cc supply voltage v cc supply voltage (v) 3 maximum duty cycle (%) 75 80 85 4.5 5.5 3802 g20 70 65 0 3.5 4 5 90 95 100 6 t a = 25 c f sw = 550khz v cmpin > 0.54v v cmpin < 0.54v switching frequency (khz) 330 maximum duty cycle (%) 95 510 3802 g21 80 70 390 450 570 65 60 100 90 85 75 630 690 750 t a = 25 c v cc = 5v v cmpin > 0.54v v cmpin < 0.54v v comp (v) 0.8 0 duty cycle (%) 10 30 40 50 100 70 1.2 1.6 1.8 3802 g22 20 80 90 60 1 1.4 2 2.2 2.4 t a = 25 c v cc = 5v v cmpin = v fb v in = 5v v in = 30v v in = 20v v in = 12v maximum duty cycle vs switching frequency duty cycle vs v comp i imax and i run/ss vs temperature i imax vs v cc supply voltage driver supply current vs load temperature ( c) ?0 i imax ( a) i run/ss ( a) 11.5 25 3802 g23 10.0 9.0 ?5 0 50 8.5 8.0 12.0 11.0 10.5 9.5 15 0 ?0 ?5 ?0 20 10 5 ? 75 100 125 v cc = 5v i imax i run/ss sink current i run/ss source current v cc supply voltage (v) 3 8.5 i imax ( a) 9.1 9.7 10.3 10.9 11.5 3.5 4 4.5 5 3802 g24 5.5 6 t a = 25 c c tg , c bg load (pf) 0 driver supply current (ma) 40 60 i pvcc i boost1 i boost2 8000 3802 g25 20 0 2000 4000 6000 10000 80 t a = 25 c pv cc = v boost ?v sw = 5v
ltc3802 8 3802f typical perfor a ce characteristics uw supply current vs temperature supply current vs supply voltage temperature ( c) ?0 25 supply current (ma) 0.1 1 10 0 25 50 75 100 125 3802 g26 0.01 i vcc i pvcc (no load) i vcc shutdown i boost1 i boost2 (no load) v cc = v pvcc = v boost ?v sw = 5v supply voltage (v) 3 0.01 supply current (ma) 1 10 45 3.5 4.5 5.5 6 3802 g27 0.1 t a = 25 c i vcc i pvcc (no load) i vcc shutdown i boost1, i boost2 (no load) pi fu ctio s uuu (28-pin ssop/32-pin qfn package) pv cc (pin 1/pin 29): driver power supply input. pv cc provides power to the two bg drivers and must be con- nected to an external voltage high enough to fully turn on the external mosfets, qb1 and qb2. pv cc requires at least a 10 m f bypass capacitor directly to pgnd. bg1 (pin 2/pin 30): channel 1 controller bottom gate drive. the bg1 pin drives the gate of the bottom n-channel synchronous switch mosfet, qb1. bg1 is designed to drive typically up to 10,000pf of gate capacitance. boost1 (pin 3/pin 31): channel 1 controller top gate driver supply. boost1 should be bootstrapped to sw1 with a 0.1 m f capacitor. an external schottky diode from pv cc to boost1 creates a complete floating charge- pumped supply at boost1. no other external supplies are required. tg1 (pin 4/pin 32): channel 1 controller top gate drive. the tg1 pin drives the top n-channel mosfet with a voltage swing equal to pv cc superimposed on the switch node voltage sw1. tg1 is designed to drive typically up to 6000pf of gate capacitance. sw1 (pin 5/pin 1): channel 1 controller switching node. connect sw1 to the switching node of the channel 1 converter. when the bottom mosfet qb1 turns on, the current limit comparator and the burst comparator monitor the voltage at sw1. if the voltage drop across mosfet qb1 is too large, the controller enters current limit; if it is too small, the switcher enters burst mode operation. see current limit and burst mode applica- tions information. pgnd (pin 6/pins 2, 3, 23, 24): power ground. the bg drivers return to this pin. connect pgnd to a high current ground node in close proximity to the sources of external mosfets qb1 and qb2 and the v in , pv cc and v out bypass capacitors. i max1 (pin 7/pin 4): channel 1 controller current limit set. the i max1 pin has an internal 10 m a current source pull-up, allowing the current limit and burst comparator threshold to be programmed by a single external resistor to sgnd. see current limit and burst mode applications information.
ltc3802 9 3802f fbt (pin 8/pin 5): feedback tracking input. fbt should be connected through a resistive divider network to v out1 to set the channel 1 output slew rate. upon power-up/-down, the ltc3802 servos fbt and cmpin2 to the same poten- tial to control the output power-up/-down slew rate. to program both outputs to have the same slew rate, dupli- cate the cmpin2 resistive divider at fbt. to have a ratiometric slew rate, short fbt to cmpin1. to disable the tracking function, short fbt to cmpin2. cmpin1 (pin 9/pin 6): channel 1 controller comparators input. cmpin1 should be connected through a resistive divider network to v out1 to monitor its real time output voltage. to improve transient response, a feedforward capacitor can be added to the resistive divider. the power good comparators, overvoltage comparator and burst reset comparators monitor this node directly. cmpin1 is a sensitive pin, avoid coupling noise into this pin. comp1 (pin 10/pin 7): channel 1 controller error ampli- fier output. the comp1 pin is connected directly to the channel 1 error amplifier output and the input of the line feedforward circuit. use an rc network between the comp1 pin and the fb1 pin to compensate the feedback loop for optimum transient response. under start-up conditions, the potential at run/ss controls the slew rate at comp1. fb1 (pin 11/pin 8): channel 1 controller error amplifier input. fb1 should be connected through a resistive divider network to v out1 to set the channel 1 switcher output voltage. also, connect the channel 1 switcher loop com- pensation network to fb1. sgnd (pin 12/pin 9): signal ground. all the internal low power circuitry returns to the sgnd pin. connect to a low impedance ground, separated from the pgnd node. all feedback, compensation and soft-start connections should return to sgnd. sgnd and pgnd should be connected only at a single point, near the pgnd pin and the negative terminal of the v in bypass capacitor. pi fu ctio s uuu (28-pin ssop/32-pin qfn package) fcb (pin 13/pin 10): force continuous bar. internally pulled high. when fcb is shorted to gnd, the controller forces both converters to maintain continuous synchro- nous operation regardless of load current. extref (pin 11, qfn package only): external reference. the extref pin and the internal bandgap voltage are used as the switcher control loops reference in a diode or manner. if the potential at the extref pin is less than 0.6v, it overrides the internal reference and lowers the switcher output voltages. if extref potential is more than 1v, the internal bandgap voltage controls both channel output voltages. extref has no effect on the pgood threshold. extref is internally connected to the run/ss pin in the gn28 package. run/ss (pin 14/pin 12): run control and soft-start input. an internal 7 m a current source pull-up and an external capacitor to ground at this pin sets the start-up delaly (approximately 300ms/ m f), the output ramp rate and the time delay for soft current limit. forcing this pin below 0.8v with an open-drain/collector transistor shuts down the device. pulling run/ss high with a current greater than 10 m a can result in malfunctioning of tracking during start-up. pulling run/ss high with currents higher than 50 m a can interfere with current limit protection. pgood (pin 15/pin 13): open-drain power good output. pgood is pulled to ground under shutdown condition or when any switcher output voltage is not within 10% of its set point . v inff (pin 16/pin 14): line feedforward compensation input. connects to the v in power supply to provide line feedforward compensation. a change in v in immediately modulates the input to the pwm comparator and changes the pulse width in an inversely proportional manner, thus bypassing the feedback loop and providing excellent tran- sient line regulation. v inff is a sensitive pin, an external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain.
ltc3802 10 3802f pi fu ctio s uuu (28-pin ssop/32-pin qfn package) phasemd (pin 17/pin 15): phase selector input. this pin determines the phase relationships between controller 1, controller 2 and the pllin signal. when phasemd is floating, its value is around 2v, and the internal phase- locked loop synchronizes the falling edge of tg1 to the falling edge of the pllin signal. when phasemd is forced high, pllin leads tg1 by 90 . tg1 and tg2 remain at 180 out of phase independent of the phasemd input. when phasemd is forced low, an internal current source dis- charges the run/ss slowly to provide power down track- ing. avoid coupling noise into this sensitive pin. fb2 (pin 18/pin 16): channel 2 controller error amplifier input. see fb1. comp2 (pin 19/pin 17): channel 2 controller error am- plifier output. see comp1. v cc (pin 20/pin 18): power supply input. all the internal circuits except the switcher output drivers are powered from this pin. v cc should be connected to a low noise 5v supply and should be bypassed to sgnd with at least a 10 m f capacitor in close proximity to the ltc3802. cmpin2 (pin 21/pin 19): channel 2 controller compara- tors input. see cmpin1. i max2 (pin 22/pin 20): channel 2 controller current limit set. see i max1 . plllpf (pin 23/pin 21): phase-locked loop lowpass filter. the phase-locked loops lowpass filter is tied to this pin. alternatively, this pin can be driven with an ac or dc voltage source to vary the frequency of the internal oscillator. pllin (pin 24/pin 22): phase-locked loop input/exter- nal synchronization input to the phase detector. the falling edge of this signal is used for frequency synchro- nization. when pllin floats or shorts to ground, the controllers free run at 550khz. sw2 (pin 25/pin 25): channel 2 controller switching node. see sw1. tg2 (pin 26/pin 26): channel 2 controller top gate drive. see tg1. boost2 (pin 27/pin 27): channel 2 controller top gate driver supply. see boost1. bg2 (pin 28/pin 28): channel 2 controller bottom gate drive. see bg1. exposed pad (pin 33, qfn package only): exposed pad is pgnd, must be soldered to pcb.
ltc3802 11 3802f block diagra w + + burst + max v ref + 5% v ref ?12mv v ref + 15mv + neg reset + pos reset + err i lim 5 100 logic stop top gate disable burst mode operation sgnd 10 a ? power down i max1,2 pgnd bg1, 2 pv cc sw1, 2 tg1, 2 fcb channel 1 subcircuit duplicate for second controller channel v cc boost1, 2 + pwm line feedforward compensation soft- start 100 s delay from ch2 pgood comparators pll and osc pllin to ch2 plllpf v inff comp1, 2 phasemd extref (qfn package only) fb1, 2 pgood mpg v ref 0.6v 7 a run/ss fbt cmpin1, 2 3802 bd v ref ?10% cmpin2 + v ref + 10% pgood comparators + track npg + ppg
ltc3802 12 3802f applicatio s i for atio wu uu switching architecture the ltc3802 includes two step-down (buck) voltage mode feedback switching regulator controllers. these two controllers act independently of each other except at start- up and current limit. for proper power-up sequencing, channel 1 is designated to be the higher output voltage channel (see start-up tracking). each channel uses two external sychronous n-channel mosfets. a floating topside driver and a simple external charge pump provide full gate drive to each upper mosfet. the controller uses leading edge modulation architecture to allow extremely low duty cycle and fast load recovery operation. in a typical ltc3802 switching cycle, the pwm comparator turns on the top mosfet and charges up the output capacitor. some time later, an internal clock resets the top mosfet, turns on the bottom mosfet and re- duces the output charging current. the top gate duty cycle is controlled by the feedback amplifier, which compares the divided output voltage with an internal reference. this switching cycle repeats itself at a fixed 550khz frequency or in synchronization with an external oscillator. the internal master clock runs at 550khz, turning off the top gate once every 1.8 m s. thus, feedback loop compo- nents and output inductors and capacitors can be scaled to a particular operating frequency. noise generated by the circuit will always be in a known frequency band, with the 550khz frequency designed to leave the 455khz if band free of interference. subharmonic oscillation and slope compensation, common headaches with constant fre- quency current mode switchers, are absent in voltage mode designs like the ltc3802. two ltc3802 channels run from a common clock, with the phasing chosen to be 180 from channel 1 to channel 2. this has the effect of doubling the frequency of the switching pulses seen by the input bypass capacitor, significantly lowering its rms current and reducing the capacitance required. feedback control each ltc3802 channel senses the output voltage at v out with an internal feedback op amp (see block diagram). this is a real op amp with a low impedance output, 80db open-loop gain and 10mhz gain-bandwidth product. the positive input is connected to a level-shifted internal 600mv reference, while the negative input is connected to the level-shifted fb pin. the output is connected to comp, which is in turn connected to the line feedforward circuit and from there to the pwm generator. to speed up the overshoot recovery time, the maximum potential at the comp pin is internally clamped at a level corresponding to the maximum top gate duty cycle. under start-up condi- tions, run/ss controls the comp pin slew rate. at steady state, as shown in figure 1, the output of the switching regulator is given the following equation vv r r out ref b =+ ? ? ? ? 1 1 unlike many regulators that use a transconductance (g m ) amplifier, the ltc3802 is designed to use an inverting sum- ming amplifier topology with the fb pin configured as a virtual ground. this allows the feedback gain to be tightly controlled by external components, which is not possible with a simple g m amplifier. in addition, the voltage feed- back amplifier allows flexibility in choosing pole and zero locations. in particular, it allows the use of type 3 com- pensation, which provides a phase boost at the lc pole frequency and significantly improves the control loop phase margin. in a typical ltc3802 circuit, the feedback loop consists of the line feedforward circuit, the modulator, the external inductor, the output capacitor and the feedback amplifier with its compensation network. all these components affect loop behavior and need to be accounted for in the loop compensation. the modulator consists of the pwm generator, the output mosfet drivers and the external mosfets themselves. the modulator gain varies linearily with the input voltage. the line feedforward circuit com- pensates for this change in gain, and provides a constant gain from the error amplifier output to the inductor input regardless of input voltage. from a feedback loop point of view, the combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from comp to the inductor input and has a gain roughly equal to 22v/v. it has fairly benign ac behavior at typical loop compensation frequencies with significant phase shift appearing at half the switching frequency.
ltc3802 13 3802f the external inductor/output capacitor combination makes a more significant contribution to loop behavior. these components cause a second order lc roll-off at the output with 180 phase shift. this roll-off is what filters the pwm waveform, resulting in the desired dc output voltage, but this phase shift causes stability issues in the feedback loop and must be frequency compensated. at higher frequen- cies, the reactance of the output capacitor will approach its esr, and the roll-off due to the capacitor will stop, leaving C 20db/decade and 90 of phase shift. figure 1 shows a type 3 amplifier. the transfer function of this amplifier is given by the following equation: v v sc r s r r c sr c c s c c r sc r comp out = + () ++ [] + () + [] + () () (// ) 1121 133 11 21 1 2 21 33 the rc network across the error amplifier and the feedforward components r3 and c3 introduce two pole- zero pairs to obtain a phase boost at the system unity gain frequency, f c . in theory, the zeros and poles are placed symmetrically around f c , and the spread between the zeros and the poles is adjusted to give the desired phase boost at f c . however, in practice, if the crossover fre- quency is much higher than the lc double-pole frequency, this method of frequency compensation normally gener- ates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. if conditional stability is a concern, move the error amplifiers zero to a lower frequency to avoid excessive phase dip. the following equations can be used to com- pute the feedback compensation components value: f switching frequency f lc f rc sw lc out esr esr out = = p = p 1 2 1 2 choose: required error amplifier gain at frequency f c : ?+ ? ? ? ? + ? ? ? ? () ? + ? ? ? ? ++ ? ? ? ? ++ ? ? ? ? 40 1 20 1 20 20 2 1 11 1 22 222 2 log log log log () () () () f f f f a r r f f f f ff f f f f ff c lc c esr mod lc c p res c p res z res z res c esr lc esr lc 1 1 2 + ? ? ? ? f f p res c () where a mod is the modulator and line feedforward gain and is equal to: a vdc v vv mod in max max saw ?=? () . . / 30 0 89 12 22 once the value of resistor r1, poles and zeros location have been decided, the value of r2, c1, c2, r3 and c3 can be obtained from the above equations. applicatio s i for atio wu uu figure 1. type 3 amplifier compensation + v out v ref r1 r3 c3 r2 c1 gain (db) c2 fb r b comp freq ? ? +1 gain phase boost 0 phase (deg) ?0 ?80 270 380 3802 f01 f crossover frequency f ff rc f f rrc ff rc c ff rc c sw zerr lc zres c p err esr p res c == == p == p+ () == p == p 10 1 221 5 1 2133 1 221 2 5 1 233 1 2 1 2 () () () () (// )
ltc3802 14 3802f cmpin is also used as the input for the positive power good comparator ppg and the negative power good comparator npg. the ppg comparator goes high if the potential at cmpin is 10% above the nominal value. the npg compara- tor fires if cmpin potential is 10% lower than the nominal value. the output of ppg and npg is connected to the pgood pin through the transistor mpg (see block dia- gram). pgood is an open-drain output and requires an external pull-up resistor. if channel 1 and 2 regulator out- put voltages are within 10% of their nominal values, the transistor mpg shuts off and pgood is pulled high by the external pull-up resistor. if any of the two outputs is out- side the 10% window for more than 100 m s, pgood pulls low indicating that at least one output is out of regulation. for pgood to go high, both switcher outputs must be in regulation. pgood remains active during soft-start and cur- rent limit. upon power-up, pgood is forced low. as soon as the run/ss pin rises above the shutdown threshold, the power good comparators take over and control the transis- tor mpg directly. the 100 m s delay ensures that short out- put transient glitches that are successfully caught by the power good comparators dont cause momentary glitches at the pgood pin. current limit protection the ltc3802 includes an onboard current limit circuit that limits the maximum output current to a user-programmed level. it works by sensing the voltage drop across qb when qb is on and comparing that voltage to a user-pro- grammed voltage at i max . the i max pin includes a trimmed 10 m a pull-up, enabling the user to set the voltage at i max with a single resistor, r imax , to ground. the current comparator reference input is equal to v imax divided by 5 (see block diagram). any time qb is on and the current flowing to the output is reasonably large, the sw node at the drain of qb will be somewhat negative with respect to pgnd. since qb looks like a low value resistor during its on-time, the voltage drop across it is proportional to the current flowing in it. the ltc3802 senses this voltage, inverts it and compares it to the current comparator reference. the current com- parator begins limiting the output current when the mag- nitude of the negative voltage is larger than its reference. applicatio s i for atio wu uu compensating a switching power supply feedback loop is a complex task. the applications shown in this data sheet show typical values, optimized for the power components shown. though similar power components should suf- fice, substantially changing even one major power com- ponent may degrade performance significantly. stability also may depend on circuit board layout. to verify the calculated component values, all new circuit designs should be prototyped and tested for stability. overvoltage protection and power good flag notice that the fb pin is the feedback amplifiers virtual ground node (offset by v ref ). because the typical com- pensation network does not include local dc feedback around the amplifier, the dc level at fb will be an accurate replica of the output voltage, divided down by the resistive divider. however, the compensation capacitors will tend to attenuate ac signals at fb, especially during quick transients. because of this delay in the servo loop, the duty cycle is not able to adjust immediately to shifts in the output voltage. this problem is most apparent at high input and low output voltages. under transient conditions, a slow reaction in the duty cycle could cause a large step in the output voltage. the ltc3802 avoids this voltage instability through the use of an additional comparator input pin, cmpin, which provides real time measurement of the output voltage. a duplicate fb divider, r1 and r b should be connected to this pin. a small feedforward capacitor can be added across the top resistor to speed up the comparators. the max comparator monitors the output voltage through the cmpin pin. if the output moves 5% above its nominal value, the comparator immediately turns the top mosfet (qt) off and the bottom mosfet (qb) on and maintains this state until the output falls back within 5% of its nomi- nal value. this pulls the output down as fast as possible, preventing damage to the (often expensive) load. if cmpin rises because the output is shorted to a higher supply, qb will stay on until the short goes away, the higher supply current limits or qb dies trying to save the load. this be- havior provides maximum protection against overvoltage fault at the output, while allowing the circuit to resume normal operation when the fault is removed.
ltc3802 15 3802f the current limit detector is connected to an internal 100 m a current source. once current limit occurs, this current begins to discharge the soft-start capacitor at run/ss, reducing the duty cycle and controlling the output voltage until the current drops below the limit. the soft-start capacitor needs to move a fair amount before it has any effect on the duty cycle, adding a delay until the current limit takes effect. this allows the ltc3802 to experience brief overload conditions without affecting the output voltage regulation. the delay also acts as a pole in the current limit loop to enhance loop stability. under severe short-circuit conditions, if the load current is 1.5 times larger than the programmed current limit thresh- old, the ltc3802 shuts off the top mosfet immediately. this stops the increase in the inductor current. at this moment, if cmpin is 10% lower than its nominal value, the ltc3802 hard current limit latches and discharges the run/ss capacitor with a current source of more than 1ma until run/ss hits its shutdown threshold. once run/ss is completely discharged, the ltc3802 cycles its soft- start again. programming the current limit on the ltc3802 is straight- forward. to set the current limit, calculate the expected voltage drop across qb at the maximum desired current: v prog = (i limit )(r ds(on) ) i limit should be set much higher than the expected oper- ating current, to allow for mosfet r ds(on) changes with temperature. power mosfet r ds(on) varies from mosfet to mosfet, limiting the accuracy obtainable from the ltc3802 current limit loop. setting i limit to 150% of the maximum normal operating current is usually safe and will adequately protect the power components if they are chosen properly. note that ringing on the switch node can cause an error for the current limit threshold. this factor will change depending on the layout. the sw node should have minimum routing from the mosfets to the ltc3802 to reduce parasitic inductor and hence ringing. v prog is then programmed at the i max pin using the internal 10 m a pull-up current and an external resistor: r v a imax prog = m 5 10 the resulting value of r imax should be checked in an actual circuit to ensure that the current circuit kicks in as expected. circuits that use very low values for r imax (<25k) should be checked carefully, since small changes in r imax can cause large i limit changes when the switch node ringing makes up a large percentage of the total v prog value. if v prog is set too low, the ltc3802 may fail to start up. the ltc3802 current limit is designed prima- rily as a disaster preventing, no blow up circuit, and is not useful as a precision current regulator. the ltc3802 bottom mosfet v ds current sensing archi- tecture not only eliminates the external current sense resistors and the corresponding power losses in the high current paths, it allows a wide range of output voltage setting, including extremely low duty cycle operation. on the other hand, for high input voltage with small output inductance applications, care must be taken to avoid inductor saturation during dead-short conditions. as soon as the output short circuits, the controller instantaneously enters maximum duty cycle operation. during the top mosfet on interval, the current compara- tor is not monitoring the current and there is no current limit action until the bottom mosfet turns on and the inductor current exceeds its hard current limit threshold. typically, the top mosfet and the inductor need to withstand one clock period of transient high current op- eration until the hard current limit operation engages. peak currents can exceed 6 times the maximum dc output current during this period. most mosfets allow 10 m s of high current and this short duration of current should not damage the mosfet. nevertheless, it is a good idea to reduce the peak inductor current. this can be achieved by having a larger inductance to limit the short-circuit current slew rate, or an inductor with a saturation current that is higher than the hard current limit threshold. alternatively, an inductor core material with a softer saturation charac- teristic such as iron powder can be used. shutdown/soft-start the run/ss pin performs two functions: when pulled to ground it shuts down the ltc3802, and it acts as a conventional soft-start pin, enforcing a maximum duty cycle limit proportional to the voltage at run/ss. an applicatio s i for atio wu uu
ltc3802 16 3802f internal 7 m a current source pull-up is connected to the run/ss pin, allowing a soft-start ramp to be generated with a single external capacitor to ground. the 7 m a current source is active even when the ltc3802 is shut down, ensuring the device will start when the external pull-down at run/ss is released. under shutdown conditions, the ltc3802 goes into a micropower sleep mode, and the quiescent current drops to 100 m a. the run/ss pin shuts down the ltc3802 when it falls below 0.8v (figure 2). between about 0.8v and 2v, the ltc3802 wakes up and the duty cycle is kept to a miminum. as the potential at run/ss goes higher, the duty cycle increases linearly between 2v and 3.2v, reaching its final value of 89% when run/ss exceeds 3.2v. prior to this point, the feedback amplifier will assume control of the loop and the output will come into regulation. note that the run/ss linear range varies with the potential at v inff ; for 5v input voltage, the run/ss active range reduces to 2v-2.25v. the value of the soft-start capacitor, c ss , may depend on the input and output voltages, inductor value, output capacitance and load current. the inductors start-up current (from v out = 0v), can be much higher than its steady-state current. the difference depends on the input power supply slew rate, the input and output voltages, the ltc3802 soft-start slew rate, and the inductor and output capacitor values. for a given application, the known input and output requirements determine the output inductor and capacitor values. these values establish the transient load recovery time. in general, a low value inductor combined with a high value capacitor yields a short transient load recovery time at the expense of higher inductor ripple and start-up current. these components, together with a small soft- start capacitor, can also cause high inrash current. this triggers the ltc3802 current limit comparator and forces the ltc3802 to repeat the soft-start cycle, never allowing the supply to start. start-up problems can also occur when a small soft-start capacitor is used with a small output inductor and capacitor. high input voltages generate high inrash cur- rents, charging the output capacitor quickly and causing the output to overshoot. the ltc3802 ovp comparator turns off the top mosfet once the output is 5% higher than its nominal value. however, the residual energy in the inductor will continue to charge the output capacitor, forcing the output voltage to increase further until the inductor energy is depleted. this overshoot at the output causes the feedback loop to operate nonlinearly; the output tends to ring for several cycles until the loop mechanism is restored. therefore, select c ss with start-up in mind. choosing c ss to ensure that there is no output overshoot and the inrush current is not able to trigger the current comparator. a minimum recommended soft-start capacitor of c ss = 0.1 m f will be sufficient for most applications. undervoltage lockout the ltc3802 is designed for wide v in operation. the internal uvlo circuit monitors the v cc and v inff potential and starts operation as long as they are above their 2.5v uvlo thresholds. for high v in supply operation, the low uvlo threshold should not cause any problem under typical application conditions. upon power-up, once the v in potential is higher than the uvlo threshold, the ltc3802 releases the run/ss node and allows the start- up current to charge the soft-start capacitor. the time interval for the run/ss potential to ramp from 0.8v to 2v allows the v in supply to slew to its steady-state potential. a 0.1 m f soft-start capacitor creates a 17ms time delay before the driver starts switching. most power supplies have a start-up time well within this time interval. for some applicatio s i for atio wu uu figure 2. soft-start operation in start-up and current limit start-up run/ss 0v 5v 3.2v 2v 0.8v 0v power down mode normal operation comp controls duty cycle run/ss controls duty cycle minimum duty cycle current limit 3802 f02 v out ltc3802 enable
ltc3802 17 3802f special power supplies with a slow start-up slew rate, the ltc3802 drivers might start switching before the input supply reaches its steady-state value. the high inrush current through the input power cable might cause the v in supply to dip below the uvlo threshold and cause start- up problems. figure 3 shows a simple circuit to fix this problem. the selection of the zener voltage allows the v in uvlo trip point to be programmed externally. the ltc3802 can be configured to give two different power-up/power-down slew rates to meet different appli- cation requirements: ratiometric and coincident tracking configurations (figure 4). with a ratiometric configura- tion, the ltc3802 produces two different output slew rates (with v out1 > v out2 ). because each channels slew rate is proportional to its corresponding output voltage, the two output voltages reach their steady-state value at about the same time. the coincident configuration pro- duces the same slew rate at both outputs, so that the lower output voltage channel reaches its steady state first. figure 4 shows the simplified schematic to realize this power-up function. during power-up, the tracking ampli- fier track servos the tracking feedback loop and forces fbt to be at the same potential as cmpin2. for ratiometric start-up, set: r t5 = r51 or remove resistors r t4 and r t5 and short fbt to cmpin1. at power-up, if the channel 2 output voltage slew rate is too fast, or cmpin2 is higher than fbt, the tracking amplifier will force a smaller channel 2 duty cycle. channel 1s duty cycle is controlled by the run/ss pin and is not affected by the tracking amplifier. for coincident start-up, set: r t5 = r52 during power-up, if the channel 1 output voltage is higher than that of channel 2, or if fbt is higher than cmpin2, the tracking amplifier track starts to discharge the c ss capacitor and forces both channels to have the same duty cycle and output voltage. the tracking amplifier stops discharging once channel 2 reaches its negative power good threshold. to have the proper power-down sequence, ground the phasemd pin. this turns on an internal current source which slowly discharges the soft-start capacitor. once the run/ss potential is low enough to control the duty cycle, the tracking amplifier takes control and servos the feed- back loop to produce the selected output ramp. the ltc3802 tracking function can be easily disabled by disconnecting the fbt resistive divider and shorting fbt to cmpin2. applicatio s i for atio wu uu q2 2n3904 c ss 3802 f03 100k 100k 10k v in > v z run/ss ltc3802 q1 2n3904 1n4699 v z = 12v figure 3. external uvlo setting start-up tracking many dsp chips, microprocessors, fpgas and asics require multiple power supplies for the core and i/o sections. internally, the core and i/o blocks are isolated by structures which may become forward biased if the supply voltages are not at specified levels. during power-up and power-down operations, differences in the starting point and ramp rates of the two supplies may cause current to flow between the isolation structures which, when pro- longed and excessive, can reduce the useable life of the semiconductor device. these currents can also trigger latch-up in devices, leading to device failure. of greater concern than internal isolation of core and i/o structures are system-level concerns, such as bus contention between the i/o pins of the dsp and external peripheral devices. power supply sequencing between the core and i/o may be required to prevent bidirectional i/o pins of the dsp and a peripheral device from opposing each other. since the bus control logic originates in the core section, powering the i/o prior to the core may cause the dsp and peripheral pins to be configured simulatneously as outputs. if the data values on each side are opposing, then the output drivers contend for control, causing excessive current flow and eventually device failure.
ltc3802 18 3802f the qfn version of the ltc3802 provides an additional reference pin for external ratiometric start-up. if the poten- tial at the extref pin is less than 0.6v, it overrides the internal reference. this pin can be connected to an external ramp to control the output slew rate. if external tracking is not required, connect extref to a potential somewhat larger than 0.6v or short extref to the run/ss pin. the extref pin should never be allowed to float. in the gn28 package, extref is internally shorted to the run/ss pin. burst mode operation the ltc3802 switcher supply has two modes of opera- tion. under heavy loads, it operates as a fully synchro- nous, continuous conduction switching regulator. in this mode of operation (continuous mode), the current in the inductor flows in the positive direction (towards the out- put) during the entire switching cycle, constantly supply- ing current to the load. in this mode, the synchronous switch (qb) is on whenever qt is off, so the current always flows through a low impedance switch, minimizing volt- age drop and power loss. this is the most efficient mode of operation at heavy loads, where the resistive losses in the power devices are the dominant loss term. continuous mode works efficiently when the load current is greater than half of the ripple current in the inductor. in a buck converter like the ltc3802, the average current in the inductor (averaged over one switching cycle) is equal to the load current. the ripple current is the difference between the maximum and the minimum current during a switching cycle (see figure 5a). the ripple current depends on inductor value, clock frequency and output voltage, but is constant regardless of load as long as the ltc3802 remains in continuous mode. see the inductor selection section for a detailed description of ripple current. applicatio s i for atio wu uu figure 4. simplified power-up/power-down output tracking schematic 1.7v saw1 phasemd track c ss power-up/-down outputs run/ss saw2 l2 l1 extref c out1 v out1 r11 r t4 r b1 cmpin1 fbt r t5 ref + + ch2 duty cycle control lff and pwm v out1 must be higher than v out2 r11 = r41 = r t4 = r12 = r42 r b1 = r51, r b2 = r52 extref c out2 v out2 ref cmpin2 3802 f04 r12 7 a 14 a r42 r b2 r52 + r41 r51 + + lff and pwm ch1 duty cycle control + ratiometric tracking r t5 = r51 c ss = 1 f v out1 with 10 load v out2 with 10 load 0.5v/div 10ms/div coincident tracking r t5 = r52 c ss = 1 f v out1 with 10 load v out2 with 10 load 0.5v/div 10ms/div
ltc3802 19 3802f to minimize the switching loss and reverse current flow at light loads, the ltc3802 switches to a second mode of operation: burst mode operation (figure 5b). in burst mode operation, at the end of the qb cycle, if the inductor current approaches zero or goes negative, the ltc3802 turns off both drivers. the actual cutoff threshold is proportional to the i max setting and is equal to: v mv imax 100 3 the C3mv built-in offset overcomes the random mis- match in the burst compararator trip point and allows burst mode operation at no load. once both mosfets shut off, the voltage at the sw pin will float around v out , and the inductor current and the voltage across the inductor will be close to zero. this prevents current from flowing backwards in qb, eliminating that power loss term. the moment the ltc3802 enters burst mode operation, both drivers skip a number of switching cycles until the internal 36 m s timeout forces the switcher to return to continuous operation. this timeout eliminates the audible noise from certain types of inductors when they are lightly loaded. after the 36 m s timeout, the ltc3802 forces one continuous mode cycle and checks the inductor current at the end of the period. if it is still too small, it enters burst mode operation again. this pattern repeats until the out- put is loaded. the ltc3802 returns to continuous mode operation if it detects that cmpin potential is 12mv below or 15mv above its nominal bandgap voltage. immediately after returning to continuous mode operation, the regula- tor output might continue to droop slightly until the feed- back loop responds and requests an increase in duty cycle. during sudden transient steps, the regulator output ripple is limited by the feedback loop transient response and is independent of the mode of operation. the small 15mv and C12mv offset at the pos and neg reset comparators ensure that after a transient load step, the ltc3802 returns to continuous mode quickly. this minimizes the output ripple under burst mode operation. for proper burst mode operation, the ltc3802 requires very precise cmpin and fb sensing. to realize this, cmpin and fb must use the same resistive divider values applicatio s i for atio wu uu as the output load current decreases in continuous mode, the average current in the inductor will reach a point where it drops below half the ripple current. at this point, the current in the inductor will reverse during a portion of the switching cycle, or begin to flow from the output back to the input. this does not adversely affect regulation, but does cause additional losses as a portion of the inductor current flows back and forth through the resistive power switches, giving away a little more power each time and lowering the efficiency. there are some benefits to allow- ing this reverse current flow: the circuit will maintain regulation even if the load current drops to zero and the output ripple voltage and frequency remain constant at all loads, easing filtering requirements. however, continuous mode at low output current does cause losses in effi- ciency. a portion of the inductor current flows back and forth through the resistive power switches, causing i 2 r losses. the drivers continue to switch qt and qb on and off once a cycle. each time an external mosfet is turned on, the internal driver must charge its gate to a potential above the mosfets source voltage; when the mosfet is turned off, that charge is lost to ground or sw. at the high switching frequencies, the lost gate charges can add up to tens of millicoulombs. as the load current continues to drop, these charges quickly become the dominant power loss term, reducing efficiency once again. figure 5a. continuous mode figure 5b. burst mode operation inductor current i ripple 3802 f05a i average time inductor current i ripple time 3802 f05b i average
ltc3802 20 3802f and all resistors should have better than 1% tolerance. if this is not possible and burst mode operation is required, the potential at cmpin can be set slightly higher than fb by using a slightly bigger resistor from cmpin to ground. this removes the requirement of having expensive resis- tors at the fb and cmpin pins, at the expense of having a higher burst mode ripple and slightly different overvolt- age and power good thresholds. to ensure clean burst mode operation, the cmpin and fb resistive divider re- quires good layout technique. both resistive dividers must be connected to the same nodes and away from high current paths. low load current efficiency depends strongly on proper burst mode operation. in an ideal system, the gate drive is the dominant loss term at low load currents. burst mode operation turns off all output switching for several clock cycles in a row, significantly cutting gate drive losses. as the load current in burst mode operation falls toward zero, the current drawn by the ltc3802 falls to a quiescent levelabout 6.5ma. to maximize low load efficiency, make sure the ltc3802 is allowed to enter burst mode operation as cleanly as possible. operating frequency/frequency synchronization the ltc3802 controller uses a constant frequency, phase- lockable internal oscillator with its frequency determined by an internal capacitor. this capacitor is charged by a fixed current plus an additional current that is proportional to the voltage applied to the plllpf pin. when the pllin pin is not used, an internal pull-down current source forces pllin to ground and the controller runs at a fixed 550khz switching frequency. the phase-locked loop allows the internal oscillator to be synchronized to an external source via the pllin pin. the phase-locked loop consists of an internal voltage con- trolled oscillator, a divide by 12 frequency divider and a phase detector. the voltage controlled oscillator monitors the output of the phase detector at the plllpf pin. it provides a linear relationship between the plllpf poten- tial and the master oscillator frequency. a dc voltage input from 0.5v to 1.9v corresponds to a 330khz to 750khz master switching frequency. the phase detector used is an edge sensitive digital circuit which provides zero degree phase shift between the exter- nal and internal oscillators. this type of phase detector will not lock up on an input frequency close to the harmonics of the vco center frequency. the output of the phase detector is a complementary pair of current sources charging or discharging the external filter network on the plllpf pin. a simplified block diagram is shown in figure 6. if the external frequency, f pllin , is greater than the oscil- lator frequency, f osc , current is sourced continuously, pulling up the plllpf pin. when f pllin is less than f osc , current is sunk continuously, pulling down the plllpf pin. if f pllin and f osc are the same but exhibit a phase difference, the current sources turn on for a period corre- sponding to the phase difference. thus the voltage on the plllpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase comparator output is open and the filter capacitor, c lp , holds the voltage. when locked, the pll aligns the turn off of the top mosfet to the falling edge of the synchronizing signal. the loop filter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components, c lp and r lp , determine how fast the loop acquires lock. typically r lp = 10k and c lp is between 0.01 m f and 0.1 m f. the phasmd pin determines the relative phases between the tg1, tg2 and the pllin signals. when phasemd is applicatio s i for atio wu uu figure 6. phase-locked loop block diagram v cc ltc3802 plllpf r lp c lp 3806 f06 vco internal master clock 12 phasemd pllin phase detector
ltc3802 21 3802f floating, it sits at around 2v and the internal phase-locked loop synchronizes tg1s falling edge to the falling edge of the pllin signal. when phasemd is high, these two signals are 90 out of phase. tg1 and tg2 remains 180 out of phase independent of phasemd input. the phasemd signal together with the pll circuit can be used to synchronize an additional ltc3802 power supply circuit to provide a 4-phase, 4-output solution. compared to an in-phase multiple controller solution, the ltc3802s 4-phase design reduces the input capacitor ripple current requirements and efficiency losses because the peak current drawn from the input capacitor is spaced out within the switching cycle. external components selection v cc and pv cc power supplies power for the top and bottom mosfet drivers is derived from the pv cc pin; the internal controller circuitry is de- rived from the v cc pin. under typical operating conditions, the total current consumption at these two pins should be well below 100ma. hence, pv cc and v cc can be connected to an external auxiliary 5v power supply. if an auxiliary supply is not available, a simple zener diode and a darlington npn buffer can be used to power up these two pins as shown in figure 7. to prevent switching noise from cou- pling to the sensitive analog control circuitry, v cc should have a 10 m f bypassed capacitor close to the device. the bicmos process that allows the ltc3802 to include large on-chip mosfet drivers also limits the maximum pv cc and v cc voltage to 7v. this limits the practical maximum auxiliary supply to a loosely regulated 7v rail. if v cc drops below 2.5v or pv cc drops below v cc by more than 1v, the ltc3802 goes into undervoltage lockout and prevents the power switches from turning on. top mosfet driver supply an external bootstrap capacitor, c cp , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode dcp from pv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + pv cc . the boost capacitor needs to store about 100 times the gate charge required by the top mosfet. in most applications a 0.1 m f to 1 m f, x5r or x7r dielectric capacitor is adequate. power mosfet selection the ltc3802 requires two external n-channel power mosfets, one for the top (main) switch and one for the bottom (synchronous) switch. important parameters for the power mosfets are the threshold voltage v (gs)th , breakdown voltage v (br)dss , maximum current i ds(max) , on-resistance r ds(on) and input capacitance. the gate drive voltage is set by the 5v pv cc supply. consequently, logic-level threshold mosfets must be used in ltc3802 applications. if the pv cc voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be considered. pay close attention to the v (br)dss specification, because most logic-level mosfets are limited to 30v or less. the mosfets selected should have a v (br)dss rating greater than the maximum input voltage and some margin should be added for transients and spikes. the mosfets selected should also have an i ds(max) rating of at least two times the maximum power stage output current. still, this may not be a sufficient margin so it is advisable to calculate the mosfets junc- tion temperature to ensure that it is not exceeded. the ltc3802 uses the bottom mosfet as the current sense element, particular attention must be paid to its applicatio s i for atio wu uu figure 7. ltc3802 power supply inputs + + boost tg sw bg pv cc pgnd v cc v inff v in c cp 0.1 f 0.1 f dcp c out v out v z 5.6v q1: zetex fzt603 v z : mm5z6v2st1 qt qb d1 l ltc3802 sgnd 3802 f07 10 f + c in r z 2k + 10 f 10 100 q1
ltc3802 22 3802f on-resistance. mosfet on-resistance is typically speci- fied with a maximum value r ds(on)(max) at 25 c. in this case, additional margin is required to accommodate the rise in mosfet on-resistance due to self heating and higher ambient temperature: r ds(on)(max) (t) = r t ? r ds(on)(max) (25 c) the r t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/ c as shown in figure 8a. for a maximum junction temperature of 100 c, using a value r t = 1.3 is reasonable. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets (figure 8b). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate- to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to- source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufac- turers data sheet and divide by the stated v ds voltage specified. c miller is the most important selection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: top gate duty cycle v v bottom gate duty cycle vv v out in in out in = = ? ? ? ? the power dissipation for the top and bottom mosfets at maximum output current are given by: p v v ir v i rc pv v v f p vv v ir top out in out max t top ds on max in out max dr miller cc th il th il sw bot in out in out max t top ds on max = () ()( ) + ? ? ? ? ()( ) + ? ? ? ? = () ()( () () ()() () () () () () ()() 2 2 2 2 11 r r ) ) where: r dr = effective top driver resistance v th(il) = mosfet data sheet specified typical gate threshold voltage at the specified drain current applicatio s i for atio wu uu figure 8a. typical mosfet r ds(on) vs temperature junction temperature ( c) ?0 r t normalized on-resistance 1.0 1.5 150 0.5 0 0 50 100 2.0 3802 f08a + v ds v in v gs miller effect q in ab c miller = (q b ?q a )/v ds v gs v + 3802 f08b figure 8b. gate charge characteristics
ltc3802 23 3802f c miller = calulated miller capacitance using the gate charge curve from the mosfet data sheet f sw = switching frequency both mosfets have conduction losses (i 2 r) while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 12v, the high current efficiency gener- ally improves with larger mosfets, while for v in > 12v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the bottom mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the bottom switch is on close to 100% of the period. schottky diode d1/d2 selection the schottky diode d1 shown in figure 7 conducts during the dead time between the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing a charge during the dead time, which can cause a modest (about 1%) efficiency loss. the diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between it and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. c in selection the input bypass capacitor in an ltc3802 circuit is common to both channels. the input bypass capacitor gets exercised in three ways: its esr must be low enough to keep the supply drop low as the top mosfets turn on, its rms current capability must be adequate to withstand the ripple current at the input, and the capacitance must be large enough to maintain the input voltage until the input supply can make up the difference. generally, a capacitor (particularly a non-ceramic type) that meets the first two parameters will have far more capacitance than is required to keep capacitance-based droop under control. the input capacitors voltage rating should be at least 1.4 times the maximum input voltage. power loss due to esr occurs not only as i 2 r dissipation in the capacitor itself, but also in overall battery efficiency. for mobile applica- tions, the input capacitors should store adequate charge to keep the peak battery current within the manufacturers specifications. the input capacitor rms current requirement is simplified by the multiphase architecture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst- case rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used to determine the maximum rms current requirement. increasing the output current drawn from the other out-of-phase controller will actually de- crease the input rms ripple current from this maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top n-channel mosfet is approximately a square wave of duty cycle v out /v in . the maximum rms capacitor current is given by: ii vvv v rms out max out in out in ? () () this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant devia- tions do not offer much relief. the total rms current is lower when both controllers are operating due to the interleaving of current pulses through the input capaci- tors. this is why the input capacitance requirement calcu- lated above for the worst-case controller is adequate for the dual controller design. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. applicatio s i for atio wu uu
ltc3802 24 3802f applicatio s i for atio wu uu medium voltage (20v to 35v) ceramic, tantalum, os-con and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks: ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge- rated; os-cons suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytics higher esr and dryout possibility require several to be used. sanyo os-con svp, svpd series; sanyo poscap tqc series or aluminum electrolytic ca- pacitors from panasonic wa series or cornel dublilier spv series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low esr and its big bulk capacitance goal for the input bypass. c out selection the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step tran- sients. the output ripple d v out is approximately bounded by: dd + ? ? ? ? v i esr fc out l sw out 1 8 where d i l is the inductor ripple current. d i l may be calculated using the equation: d= ? ? ? ? i v lf v v l out sw out in 1 since d i l increases with input voltage, the output ripple voltage is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. manufacturers such as sanyo, panasonic and cornell dublilier should be considered for high performance through-hole capacitors. the os-con semiconductor elec- trolyte capacitor available from sanyo has a good (esr)(size) product. an additional ceramic capacitor in parallel with os-con capacitors is recommended to offset the effect of lead inductance. in surface mount applications, multiple capacitors may have to be paralleled to meet the esr or transient current handling requirements of the application. aluminum elec- trolytic and dry tantalum capacitors are both available in surface mount configurations. new special polymer sur- face mount capacitors offer very low esr also but have much lower capacitive density per unit volume. in the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. several excellent output capacitor choices are the sanyo poscap tpd, poscap tpb, avx tps, avx tpsv, the kemet t510 series of surface mount tantalums,kemet ao-caps or the pana- sonic sp series of surface mount special polymer capaci- tors available in case heights ranging from 2mm to 4mm. other capacitor types include nichicon pl series and sprague 595d series. consult the manufacturer for other specific recommendations. inductor selection the inductor in a typical ltc3802 circuit is chosen prima- rily for inductance value and saturation current. the induc- tor should not saturate below the hard current limit threshold. the inductor value sets the ripple current, which is commonly chosen at around 40% of the anticipated full load current. lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency is obtained at low frequency with small ripple current. however, achieving high efficiency requires a large inductor and generates higher output voltage excursion during load transients. there is a tradeoff between component size, efficiency and operating frequency. given a specified limit for ripple current, the inductor value can be obtained using the following equation: l v fi v v out sw l max out in max = d ? ? ? ? () () 1 once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy
ltc3802 25 3802f applicatio s i for atio wu uu or kool m m ? cores. a variety of inductors designed for high current, low voltage applications are available from manu- facturers such as sumida, panasonic, coiltronics, coil- craft and toko. pc board layout checklist when laying out the printed circuit board, start with the power device. be sure to orient the power circuitry so that a clean power flow path is achieved. conductor widths should be maximized and lengths minimized. after you are satisfied with the power path, the control circuitry should be laid out. it is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. after the layout, the following checklist should be used to ensure proper operation of the ltc3802. 1. place the top n-channel mosfets qt1 and qt2 within 1cm of each other with a common drain connection at c in . do not attempt to split the input decoupling for the two channels because doing so can create a resonant loop. 2. place c in , c out , the mosfets, schottky diode and the inductor together in one compact area. 3. split the signal and power grounds. the path formed by the top and bottom n-channel mosfets, schottky diode, and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) termi- nals should be connected as close as possible to the (C ) terminals of the input capacitor by placing the capacitors next to each other. the combined ltc3802 signal ground pin and the ground return of c vcc must return to the combined c out (C) terminals. use a modified star ground technique: a low impedance, large cop- per area central grounding point on the same side of the pc board as the input and output capacitors, with tie-ins for the bottom of the v cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. 4. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposite channels voltage and current sens- ing feed back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3802 and occupy minimum pc trace area. 5. reduce the parasitic inductance at the sw and pgnd connections to allow proper burst mode operation. use multiple vias if possible. 6. use the same resistor values for the fb and cmpin resistive divider. connect these dividers to the same node: the (+) terminals of c out and signal ground. the dividers should be connected to a node away from any high current path. 7. place the v cc and pv cc decoupling capacitor close to the ic, between the v cc and the signal ground, and between pv cc and pgnd. the v cc capacitor provides a quiet supply for the sensitive analog circuits and the pv cc capacitor carries the mosfet drivers current peaks. an additional 1 m f ceramic capacitor placed immediately next to the v cc and sgnd pins can sub- stantially improve noise performance. checking transient response for all new ltc3802 pcb circuits, transient tests need to be performed to verify the proper feedback loop operation. the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to d i load ? (esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time, v out can be monitored for excessive overshoot or ringing which would indicate a stability problem. measuring transient response presents a challenge in two respects: obtaining an accurate measurement and gener- ating a suitable transient for testing the circuit. output measurements should be taken with a scope probe di- rectly across the output capacitor. proper high frequency probing techniques should be used. do not use the 6" ground lead that comes with the probe! use an adapter that fits on the tip of the probe and has a short ground clip kool m m is a registered trademark of magnetics, inc.
ltc3802 26 3802f to ensure that inductance in the ground path doesnt cause a bigger spike than the transient signal being measured. the typical probe tip ground clip is spaced just right to span the leads of a typical output capacitor. in general, it is best to take this measurement with the 20mhz bandwidth limit on the oscilloscope turned on to limit high frequency noise. note that microprocessor manufacturers typically specify ripple 20mhz, as en- ergy above 20mhz is generally radiated and not con- ducted and will not affect the load even if it appears at the output capacitor. now that we know how to measure the signal, we need to have something to measure. the ideal situation is to use the actual load for the test, switching it on and off while watching the output. if this isnt convenient, a current step generator is needed. this generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the ltc3802 and the transient generator must be minimized. figure 9 shows an example of a simple transient genera- tor. be sure to use a noninductive resistor as the load elementmany power resistors use an inductive spiral pattern and are not suitable for use here. a simple solution is to take ten 1/4w film resistors and wire them in parallel to get the desired value. this gives a noninductive resistive load which can dissipate 2.5w continuously or 250w if pulsed with a 1% duty cycle, enough for most ltc3802 circuits. solder the mosfet and the resistor(s) as close to the output of the ltc3802 circuit as possible and set up the signal generator to pulse at a 100hz rate with a 1% duty cycle. this pulses the ltc3802 with 100 m s transients 10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keeping the load resistor cool. gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .386 ?.393* (9.804 ?9.982) gn28 (ssop) 0502 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 20 21 22 23 24 25 26 27 28 19 18 17 13 14 16 15 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.191 ?0.249) .053 ?.069 (1.351 ?1.748) .008 ?.012 (0.203 ?0.305) .004 ?.009 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale u package descriptio figure 9. transient load generator pulse generator 0v to 10v 100hz, 1% duty cycle ltc3802 locate close to the output v out 10k 50 irfz44 or equivalent r load 3802 f09 applicatio s i for atio wu uu
ltc3802 27 3802f u package descriptio uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 0.23 typ (4 sides) 31 1 2 32 bottom view?xposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0603 0.50 bsc 0.200 ref 0.00 ?0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout
ltc3802 28 3802f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1530 high power synchronous step-down controller so-8 with current limit. no r sense tm required ltc1628/ltc1628-pg 2-phase, dual output synchronous step-down dc/dc constant frequency, standby 5v and 3.3v ldos, power good ltc1628-sync controllers ltc1702a dual polyphase ? synchronous step-down switching 550khz operation, no r sense , 3v v in 7v, voltage mode regulator ltc1704 550khz synchronous switching regulator controller 550khz, 25mhz gbw, voltage mode switching regulator plus linear regulator controller plus 2a linear regulator controller ltc1735 synchronous step-down dc/dc controller 3.5v v in 36v, 0.8v v out 6v, current mode ltc1778 no r sense current mode synchronous step-down up to 97% efficiency, 4v v in 36v, 0.8v v out (0.9)(v in ), controller i out up to 20a ltc3703 high input synchronous step-down controller v in 100v, 100khz to 600khz operation ltc3708 dual, 2-phase, no r sense synchronous step-down dc/dc 2-phase, no r sense controller with output tracking controller ltc3728 550khz, 2-phase dual output synchronous step-down synchronizable, current mode, 3.5v v in 36v, controller ssop and qfn packages ltc3832 high power step-down synchronous dc/dc controller constant frequency, voltage mode with current limit for low voltage operation 3v v in 8v, 0.6v v out (0.9)(v in ) polyphase is a registered trademark of linear technology corporation. no r sense is a trademark of linear technology corporation. ? linear technology corporation 2004 lt/tp 0404 1k ? printed in usa typical applicatio u 2.5v/15a and 1.8v/15a outputs with start-up tracking and external synchronization bg2 1 4 3 2 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 boost2 tg2 sw2 pllin plllpf i max2 cmpin2 v cc comp2 fb2 phasemd pgood v inff + + pv cc 0.1 f 100 2k 0.1 f 0.1 f v cc ext sync 10 f q1 zetex fzt603 5.6v mm5z6v2st1 d3 bas40-06lt1 qb1 si7884dp 2 qt2 si7884dp 1.5 f 35v 8 qt1 si7884dp c11 2200pf c31 1500pf ratiometric tracking c21 330pf r21 15k 10k 2k 10k r imax2 62k r imax1 62k 10k v cc 10 v cc r31 390 r51 3.16k c out1 , c out2 : sanyo 4tpd330m l1, l2: toko fda1254-1r0m r b1 3.16k bg1 boost1 tg1 sw1 pgnd i max1 fbt cmpin1 comp1 fb1 sgnd fcb run/ss c ss 0.1 f burst continuous d1 b340b d2 b340b l1 1 h + c out1 330 f 4v 3 + c in 22 f 35v 4 v out1 2.5v 15a v in 8v to 28v gnd r t4 10k r11 10k r t5 4.99k r41 10k 560pf c inff 0.47 f v in qb2 si7884dp 2 l2 1 h c out2 330 f 4v 3 r42 10k r12 10k r32 390 c32 1500pf v out2 1.8v 15a gnd 3802 ta02 r b2 4.99k r52 4.99k + 10 f 560pf 0.1 f c22 330pf c12 2200pf r22 15k 0 deg ltc3802 90 deg power down

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